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10 GB/s bit-synchronizer circuit with automatic timing alignment by clock phase shifting using quantum-well AlGaAs/GaAs/AlGaAs

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7 Author(s)
P. Wennekers ; Fraunhofer Inst. for Appl. Solid State Phys., Freiburg, Germany ; U. Novotny ; A. Huelsmann ; G. Kaufel
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A bit-synchronizer circuit is presented which operated up to a bit rate of Gb/s. The circuit comprises two master-slave flip -flops for data sampling, two EXCLUSIVE-OR gates for clock phase adjustment, an active signal splitter, and an EXCLUSIVE-OR gate for data transition detection. The gain of the EXCLUSIVE-OR phase comparator circuit is measured to be 302 mV/rad for a 1010-bit sequence. The margins for monotonous phase comparison are ±54° relative to the `in bit cell center' position of the sampling clock edge. The circuit is fabricated by using an enhancement/depletion 0.3 μm recessed-gate AlGaAs/GaAs/AlGaAs quantum-well FET process. The chip has a power dissipation of 230 mW at a supply voltage of 1.90 V

Published in:

IEEE Journal of Solid-State Circuits  (Volume:27 ,  Issue: 10 )