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A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune hidden-ECC scheme

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6 Author(s)
T. Suzuki ; Memory Technol. Dev. Group, Corp. Syst. LSI Dev. Div., Nagaokakyo, Japan ; Y. Yamagami ; I. Hatanaka ; A. Shibayama
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The mobile multi-media applications require to lower the operating voltage of embedded SRAMs. The ECC circuit implementation for increasing soft-error and the access timing control that tracks access delay fluctuation in memory core should be considered for the low-voltage operation. A hidden error-check-and-correction (HECC) scheme compensated the access time penalty caused by the ECC logic on the output critical path. And a multi-column ECC word assignment (MCE) increased the multi-bit-error immunity while using only 1-bit-correctable ECC which minimized area penalty. A source-level-adjusted direct sense amplifier (SLAD) and a write-replica circuit with an asymmetrical replica memory cell (WRAM) for the device-fluctuation-tolerant access control were also designed. A 130-nm CMOS 32-Kbit SRAM-macro was fabricated with these circuit techniques, which demonstrated: 1) 0.3-V operation with 6.8 MHz; 2) 30-MHz operation which is feasible for mobile use even at 0.4 V, while keeping 960MHz at 1.5 V; and 3) a reduction by 3.6×105 in soft-error rate compared with that of conventional ECC.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:41 ,  Issue: 1 )