Cart (Loading....) | Create Account
Close category search window
 

Concordant memory design: an integrated statistical design approach for multi-gigabit DRAM

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Akiyama, S. ; Central Res. Lab., Hitachi Ltd., Tokyo, Japan ; Sekiguchi, T. ; Kajigaya, Kazuhiko ; Hanzawa, Satoru
more authors

Concordant memory design incorporates fluctuation in device parameters statistically into signal-to-noise ratio analysis in DRAM. In this design, the effective signal voltage of all cells in a chip is calculated, and the failed bit count of the chip is estimated. The proposed design approach gives us a quantitative evaluation of the memory array and assures 1.4-V array operation of 100-nm-1-Gb DRAM. Calculated dependence of the failed bit count on the array voltage is in close agreement with measured data for the 512-Mb DRAM chip.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:41 ,  Issue: 1 )

Date of Publication:

Jan. 2006

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.