By Topic

A method for detecting interconnect DSM defects in systems on chip

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Shih-Yu Yang ; Intel Corp., Hillsboro, OR, USA ; Papachristou, Christos A.

This paper presents a built-in test method targeting interconnect defects using IDDT testing, delay testing, and boundary scan. It was learned that IDDT testing is an effective way to detect open and short defects. Boundary scan can provide accessibility to internal buses inside a chip. A statistical analysis method eases the uncertain factors due to process variations and power fluctuation. This paper also includes the experimental data using the proposed techniques to detect shorts, opens, or the other non-stuck-at fault type defects.

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:25 ,  Issue: 1 )