Skip to Main Content
Power-distribution networks of very large-scale integrated (VLSI) chips should be designed carefully to ensure reliable performance. A sound power network requires an adequate number of power-supply input connections (pads and pins). Placing them at the best vantage locations helps to reduce the number of supply connections necessary for obtaining quality power distribution. This paper addresses the problem of finding an optimum set of pads, pins, and on-chip voltage regulators, and their placement in a given power-supply network, subject to constraints on the voltage drops in the network and maximum currents through the pads, pins, and regulators. The problem is modeled as a mixed-integer linear program (MILP) with the help of macromodeling techniques. Two new heuristics, in addition to the commonly used branch-and-bound technique, are proposed to make the problem tractable. The effectiveness of the proposed technique is demonstrated on several real chips and memories used in low-power and high-performance applications.