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Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology

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2 Author(s)
B. Chatterjee ; Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Ont., Canada ; M. Sachdev

In this paper, we present the design of a 32-b arithmetic and log unit (ALU) that allows low-power operation while supporting a design-for-test (DFT) scheme for delay-fault testability. The low-power techniques allow for 18% reduction in ALU total energy for 180-nm bulk CMOS technology with minimal performance degradation. In addition, there is a 22% reduction in standby mode leakage power and 23% lower peak current demand. In the test mode, we employ a built-in DFT scheme that can detect delay faults while reducing the test-mode automatic test equipment clock frequency.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:13 ,  Issue: 11 )