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This paper presents a pre-layout inductance modeling approach for on-chip interconnect in the high-speed digital design context. Regarding the impact of the inductance on delays, assumptions on the current return path localization are compared. The influence of neighboring signal lines on the effective inductance is highlighted. Particularly, their inclusion in inductance models when the clock frequency increases is discussed. Finally, representative structure models allowing pre-layout effective inductance corner estimations are presented.
Date of Conference: 24-26 Oct. 2005