0.525/spl mu/m/sup 2/ 6T-SRAM bit cell using 45nm fully-depleted SOI CMOS technology with metal gate, high k dielectric and elevated source/drain on 300mm wafers

A low power 45nm fully-depleted SOI technology is demonstrated for the first time on 300mm SOI wafers, using direct metal gate on high k dielectric and selective silicon epitaxy. Short p-channel devices exhibit very good performance. SRAM bit cells are fully functional down to 0.525/spl mu/m/sup 2/ with good SNM and low leakage.