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0.525μm2 6T-SRAM bit cell using 45nm fully-depleted SOI CMOS technology with metal gate, high k dielectric and elevated source/drain on 300mm wafers

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31 Author(s)
Vandooren, A. ; Freescale Semicond., Crolles, France ; Hobbs, C. ; Faynot, O. ; Perreau, P.
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A low power 45nm fully-depleted SOI technology is demonstrated for the first time on 300mm SOI wafers, using direct metal gate on high k dielectric and selective silicon epitaxy. Short p-channel devices exhibit very good performance. SRAM bit cells are fully functional down to 0.525μm2 with good SNM and low leakage.

Published in:

SOI Conference, 2005. Proceedings. 2005 IEEE International

Date of Conference:

3-6 Oct. 2005