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Effect of contact liner stress in high-performance FDSOI devices with ultra-thin silicon channels and 30 nm gate lengths

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17 Author(s)
Singh, D.V. ; IBM Semicond. R&D Center, T. J. Watson Res. Center, Yorktown Heights, NY, USA ; Hergenrother, J.M. ; Sleight, J.W. ; Ren, Z.
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We have investigated for the first time the effect of stressed contact liners on the performance of fully depleted ultra-thin channel CMOS devices with a raised source/drain. Significant enhancement in mobility and drive current is observed in both nFETs and pFETs. The observed enhancement shows a strong dependence on the Si channel thickness and the height of the raised source/drain, consistent with stress simulations.

Published in:

SOI Conference, 2005. Proceedings. 2005 IEEE International

Date of Conference:

3-6 Oct. 2005

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