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Experimental characterization of source-to-drain tunneling in 10nm SOI devices

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9 Author(s)
Lolivier, J. ; CEA/DRT-LETI, Grenoble, France ; Jehl, X. ; Rafhay, Q. ; Poiroux, T.
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This work deals with the electrical characterization down to 4K of fully depleted SOI MOSFET with a physical gate length down to 10nm. Temperature measurements are used to highlight source to drain tunneling: which is evidenced at room temperature for the first time. Finally resonant tunneling effect is observed.

Published in:
SOI Conference, 2005. Proceedings. 2005 IEEE International

Date of Conference: 3-6 Oct. 2005

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