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Use of field programmable gate array technology in future space avionics

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2 Author(s)
Ferguson, R.C. ; United Space Alliance LLC, Houston, TX, USA ; Tate, R.

The existence of hardware description languages (HDLs), the recent increase in performance, density and radiation tolerance of field programmable gate arrays (FPGAs), and intellectual property (IP) cores provides the technology for reprogrammable systems on a chip (SOC). This technology supports a paradigm better suited for NASA's vision. Hardware and software production are melded for more effective development; they can both evolve together over time. To investigate the flexibility of this technology, the core of the central processing unit and input/output processor of the space shuttle AP101S computer were prototyped in Verilog HDL and synthesized into an Altera Stratix FPGA.

Published in:

Digital Avionics Systems Conference, 2005. DASC 2005. The 24th  (Volume:2 )

Date of Conference:

30 Oct.-3 Nov. 2005