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On the impact of structural circuit partitioning on SAT-based combinational circuit verification

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3 Author(s)
Herbstritt, M. ; Inst. of Comput. Sci., Albert-Ludwigs-Univ., Germany ; Kmieciak, T. ; Becker, B.

In this work we present an approach for SAT-based combinational circuit verification using partitionings of the set of primary outputs. We formally analyze the applied partitioning heuristics for the first time and present a closed verification framework incorporating traditional techniques. We report on experiments using our partitioning-based verification procedure that result in speedups of 276% on the average compared to traditional techniques.

Published in:

Microprocessor Test and Verification (MTV'04), Fifth International Workshop on

Date of Conference:

9-10 Sept. 2004