By Topic

RACE on a physically distributed and logically shared memory system

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Seongwoon Kim ; ETRI, South Korea ; Ando Ki ; Bogwan Kim

The RACE (remote access cache coherency enforcement) protocol is a cache coherency protocol that uses a full-mapped directory-based cache protocol to provide a consistent memory through multi-level memory hierarchy consisting of a number of processor caches, physically distributed shared-memory, and third level caches. In this paper, we have proposed a RACE protocol which can be used in the physically distributed and logically shared memory system.

Published in:

Systems Engineering, 2005. ICSEng 2005. 18th International Conference on

Date of Conference:

16-18 Aug. 2005