By Topic

Extended-DDF modeling embedded system design: adapting to IP technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Yi Jiao ; Dept. of Comput. & Inf. Technol., Fudan Univ., Shanghai, China ; Chenglin Guo ; Baifeng Wu ; Hui Luo

This paper extends DDF (dynamic date flow graph) to a large-grain model which can guide system design in function level. The adoption of a novel algorithm, as well as a formal definition for cDDF, strengthens the capacity of DDF as a formal specification model. Starting from a lower level of abstraction, it merges sub-modules into a larger one by extracting the input/output relations. The extracted I/O relations, together with the new module's functional description, could serve as IP core selection criteria in design space exploration. Normal DDF merely decomposes compound node into simpler ones. The algorithm presented in this paper provides a reverse process which exploits the hierarchical characteristic of DDF by capturing both data and control flow in different level of abstraction. The important steps in design work, such as function partition, scheduling, optimization, etc., are also reconsidered synthetically to adapt the introduction of the new idea.

Published in:

Computer and Information Technology, 2005. CIT 2005. The Fifth International Conference on

Date of Conference:

21-23 Sept. 2005