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Automatic test pattern generation from high level specifications

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3 Author(s)
Hassan, S. ; CSE Dept., Ain Shams Univ., Cairo, Egypt ; Wahba, A. ; Badr, A.

Tools developed for automatic test pattern generation require the circuit to be described in the form of a netlist. ATPG tools that accept circuits described in a high-level description language, such as VHDL, and generate the required test vectors, are very rare. The authors presented here a new tool that performs ATPG directly from VHDL behavioral descriptions. Performance analysis shows that the patterns generated by the behavioral ATPG tool achieve high fault coverage when tested on benchmark circuits.

Published in:

Circuits and Systems, 2003 IEEE 46th Midwest Symposium on  (Volume:3 )

Date of Conference:

27-30 Dec. 2003