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Efficient fault simulation techniques and test configuration generation for embedded FPGAs

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3 Author(s)
Shyue-Kung Lu ; Dept. of Electron. Eng., Fu Jen Catholic Univ., Taipei, Taiwan ; Hung-Chin Wu ; Yu-Cheng Tsai

With today's system-on-a-chip (SOC) technology, BIST-based techniques are the best solution for the testing of embedded FPGAs with low controllability and observability. In the past, test configurations are usually derived manually and there still lacks of an efficient fault simulator to evaluate the resulted fault coverage. Based on the BIST-based structure, an efficient fault simulator (FPGAsim) for FPGAs is proposed to alleviate it. The fault models can be updated by using a script file as well as the FPGA dimensions. Therefore, the flexibility of FPGAsim is very high. According to the regular structure during the BIST sessions, the simulation complexity can be reduced from O(N2 ) to O(1). That is, the simulation complexity is independent of the size of an FPGA. The fault simulator proposed above is also helpful for solving the following problems. 1) Given a set of target fault models, generate the required test configurations with 100% fault coverage. 2) Given a set of target fault models and a test length constraint, generate the test configurations with the highest fault coverage. 3) Set the priority of test configurations such that test length/test time can be reduced. In other words, FPGAsim can be used for generation of optimal test configurations

Published in:

Circuits and Systems, 2003 IEEE 46th Midwest Symposium on  (Volume:2 )

Date of Conference:

30-30 Dec. 2003