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A new digital background calibration technique for pipelined analog-to-digital converter (ADC) is proposed in this paper. In this architecture, two redundant pipelined stages are added to the ADC that creates time slots for the pipelined stages such that calibration cycles can be scheduled to the pipeline stages during normal operations. Compared to other background calibration techniques, the proposed technique calibrates the gain errors, the offset errors and the nonlinearity errors of the ADC. It does not need to design dedicated separate ADCs or DACs for calibration. It also provides no degradations in performance for high frequency input signals and the complexity of the digital hardware is relatively simple.
Circuits and Systems, 2003 IEEE 46th Midwest Symposium on (Volume:1 )
Date of Conference: 27-30 Dec. 2003