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An innovative free memory design for network processors in home network gateway

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3 Author(s)
Shuguang Gong ; Inst. of Comput. Technol., Chinese Acad. of Sci., Beijing, China ; Huawei Li ; Xiaowei Li

With the fast development of digital home network, the bandwidth demands of home network gateway is growing rapidly. The memory bandwidth has become the main performance bottleneck of network processor. Open-page policy and linear allocation approach have been proposed to improve the throughput of network processor through utilizing peak bandwidth of DRAM. Yet, in IC design, due to limitation of linked list memory management and IC area, the implementation of linear allocation is more complex. In this paper, a novel bitmap approach is proposed for free memory management. With efficient search architecture, compression algorithm and pre-fetch buffer, the work complexity of bitmap approach can be reduced considerably, linear allocation can be implemented easily, and memory management can also be optimized to provide high effectiveness.

Published in:

Consumer Electronics, IEEE Transactions on  (Volume:51 ,  Issue: 4 )