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Design of high-performance low-density parity-check codes using interleaver approach

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3 Author(s)
He, Z. ; Dept. of Electr. & Comput. Eng., Laval Univ., Sainte-Foy, Que., Canada ; Fortier, P. ; Roy, S.

Interleaver description of parity-check matrix is proposed for the design of high-performance low-density parity-check (LDPC) codes. Based on the S-random interleaver and the dividable S-random interleaver used in turbo codes, two classes of LDPC codes, the g-random codes and the g-random structured codes, are proposed to improve the performance in the waterfall region and slow down the onset of the error floor.

Published in:

Electronics Letters  (Volume:41 ,  Issue: 25 )