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In order to improve the stability of polysilicon thin-film transistors (TFTs) several drain junction architectures have been proposed. In this paper, the hot-carrier (HC) related stability of the lightly doped drain (LDD) TFT architecture is analyzed by using an iterative algorithm that relates the HC induced damage to the carrier injection across the device interfaces with gate and substrate oxide. The resulting creation of interface states and trapped charge is taken into account by using a system of rate equations that implements mathematically the Lais two step model, in which the generation of interface states is attributed to the trapping of hot-holes by centres into the oxide followed by the recombination with hot electrons. The rate equations are solved self-consistently with the aid of a device simulation program. By successive iterations, the time evolution of the interface state density and positive trapped charge distribution has been reconstructed, and the electrical characteristics calculated with this model are in good agreement with experimental data. This algorithm represent an improvement of an already proposed degradation model, in which the interface states formation dynamics is accounted by using a phenomenological approach. The present model has been applied to reproduce the degradation pattern of LDD TFTs and it is found that generation of interface states proceed almost symmetrically on the front and back device interfaces, starting from the points in which the transverse electric field peaks, and moving toward the drain side of the device. The final interface states distribution determines a sort of "bottleneck" in the active layer carrier density, that can explain the sensitivity to HC induced damage of both transfer and output characteristics.