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Enhanced CMOS performances using substrate strained-SiGe and mechanical strained-Si technology

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6 Author(s)
San Lein Wu ; Dept. of Electron. Eng., Kaohsiung, Taiwan ; Yu Min Lin ; Shoou Jinn Chang ; Shin Chi Lu
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We developed a novel CMOS architecture that uses mechanical tensile stress, induced by the Si nitride-capping layer, together with the pseudomorphic compressive stress in SiGe layer to improve the drive current of both n- and pMOSFETs simultaneously. The unique advantage of this process flow is that on the same wafer, individual MOSFET performance can be adjusted independently to their optimum due to the separation process for two type devices. It is found that n- and pMOSFETs in the novel CMOS architecture behaved better in performance, not only a higher drain-to-source saturation current but also higher transconductance with wide gate voltage swing, than the Si-control devices, thus making this flow to show a great flexibility for developing next-generation high-performance CMOS.

Published in:

Electron Device Letters, IEEE  (Volume:27 ,  Issue: 1 )