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A cache-defect-aware code placement algorithm for improving the performance of processors

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2 Author(s)
T. Ishihara ; Adv. CAD Technol., Fujitsu Labs. of America, Inc., Sunnyvale, CA, USA ; F. Fallah

Yield improvement through exploiting fault-free sections of defective chips is a well-known technique (Koren and Singh (1990) and Stapper et al. (1980)). The idea is to partition the circuitry of a chip in a way that fault-free sections can function independently. Many fault tolerant techniques for improving the yield of processors with a cache memory have been proposed. In this paper, we propose a defect-aware code placement technique which offsets the performance degradation of a processor with a defective cache memory. To the best of our knowledge, this is the first compiler-based technique which offsets the performance degradation due to cache defects. Experiments demonstrate that the technique can compensate the performance degradation even when 5% of cache lines are faulty. In some cases the technique was able to offset the impact even in presence of 25% faulty cache-lines.

Published in:

ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.

Date of Conference:

6-10 Nov. 2005