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A routing algorithm for flip-chip design

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5 Author(s)
Jia-Wei Fang ; Graduate Inst. of Electron. Eng., National Taiwan Univ., Taipei, Taiwan ; I-Jye Lin ; Ping-Hung Yuh ; Yao-Wen Chang
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The flip-chip package gives the highest chip density of any packaging method to support the pad-limited Application-Specific Integrated Circuit (ASIC) designs. In this paper, we propose the first router for the flip-chip package in the literature. The router can redistribute nets from wire-bonding pads to bump pads and then route each of them. The router adopts a two-stage technique of global routing followed by detailed routing. In global routing, we use the network flow algorithm to solve the assignment problem from the wire-bonding pads to the bump pads, and then create the global routing path for each net. The detailed routing consists of three stages, cross point assignment, net ordering determination, and track assignment, to complete the routing. Experimental results based on seven real designs from the industry demonstrate that the router can reduce the total wirelength by 10.2%, the critical wirelength by 13.4%, and the signal skews by 13.9%, compared with a heuristic algorithm currently used in industry.

Published in:

ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.

Date of Conference:

6-10 Nov. 2005