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A mapping algorithm for defect-tolerance of reconfigurable nano-architectures

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1 Author(s)
M. B. Tahoori ; Northeastern Univ., Boston, MA, USA

Self-assembled nano-fabrication processes yield regular and reconfigurable devices. However, defect densities in this emerging nanotechnology are higher than those in conventional lithography-based VLSI. In this paper, we present a defect-tolerant design flow to minimize customized post-fabrication design efforts to be performed per chip. We also present a greedy O(n log n) mapping algorithm which makes the connection between defect-unaware design steps and the final defect-aware step. Experiments show that the results obtained by this algorithm are very close to the exact solutions.

Published in:

ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.

Date of Conference:

6-10 Nov. 2005