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Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability

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9 Author(s)
Tsukamoto, Y. ; Renesas Technol. Corp., Itami, Japan ; Nii, K. ; Imaoka, S. ; Oda, Y.
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6T-SRAM cells in the sub-100 nm CMOS generation are now being exposed to a fatal risk that originates from large local Vth variability (σv_Local). To achieve high-yield SRAM arrays in presence of random σv_Local component, we propose worst-case analysis that determines the boundary of the stable Vth region for the SRAM read/write DC margin (Vth curve). Applying this to our original 65 nm SPICE model, we demonstrate typical behavior of the Vth curve and show new criteria for discussing SRAM array stability with Vth variability.

Published in:

Computer-Aided Design, 2005. ICCAD-2005. IEEE/ACM International Conference on

Date of Conference:

6-10 Nov. 2005