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Test planning for the effective utilization of port-scalable testers for heterogeneous core-based SOCs

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2 Author(s)
Sehgal, A. ; Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA ; Chakrabarty, K.

Many SOCs contain embedded cores with different scan frequencies. To better meet the test requirements for such heterogeneous SOCs, leading tester companies have recently introduced port-scalable testers, which can simultaneously drive groups of channels at different data rates. However the number of tester channels available for scan testing is limited; therefore, a higher shift frequency can increase the test time for a core if the resulting test access architecture reduces the bitwidth used to access it. We present a scalable test planning technique that exploits port scalability of testers to reduce SOC test time. We compare the proposed heuristic optimization method to two baseline methods based on prior work that use a single scan data rate for all the embedded cores.

Published in:

Computer-Aided Design, 2005. ICCAD-2005. IEEE/ACM International Conference on

Date of Conference:

6-10 Nov. 2005