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Rectangular cells can be flipped in place along either horizontal or vertical axis without changing the area of a layout. During floorplanning, both the location and orientation of cells are determined. However, the complexity of the floorplanning process usually means that the wirelength is not minimum. This paper proposes a technique for wirelength minimization based on in-place flipping of cells that can be applied to any floorplan style consisting of rectangular blocks or sub-blocks. Instead of conventional search procedures, a Boolean symbolic approach is proposed to generate flip-optimal floorplans. Experimental results show that it can effectively reduce the wirelength of current state of the art approaches, at no cost in area and with modest runtimes.