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This paper describes the advanced real-time processor architecture (ARPA) system-on-chip. The goal of this work is to create a technology independent and synthetizable system-on-chip (SoC) model for real-time applications. The main component of the SoC is a MIPS32-based RISC processor. It is implemented using a pipelined simultaneous multithreading structure that supports the execution of more than one thread or task at a time. The synergy between pipelining and simultaneous multithreading allows combining the exploration of Instruction level parallelism and task level parallelism, hide the context switching time and reduce the need of employing complex speculative execution techniques to improve the performance of the pipelined processor. A fundamental component of the ARPA SoC is the operating system coprocessor, which implements in hardware some of the operating systems functions, such as task scheduling, switching, communication and timing. The proposed architecture allows building flexible, high performance, time predictable and power efficient processors optimized for embedded real-time systems.