Scheduled System Maintenance on May 29th, 2015:
IEEE Xplore will be upgraded between 11:00 AM and 10:00 PM EDT. During this time there may be intermittent impact on performance. We apologize for any inconvenience.
By Topic

High-level synthesis in latency insensitive system methodology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Bomel, P. ; LESTER Lab., UBS Univ., Lorient, France ; Abdelli, N. ; Martin, E. ; Fouilliart, A.-M.
more authors

This paper presents our contribution in terms of synchronization processor to a SoC design methodology based on the theory of the latency insensitive systems (US). This methodology 1) promotes pre-developed IPs intensive reuse, 2) segments inter-IPs interconnects with relay stations to break critical paths and 3) brings robustness to data stream irregularities to IPs by encapsulation into a synchronization wrapper. Our contribution consists of IP encapsulation into a new wrapper model containing a synchronization processor, which speed and area are optimized and synthesizability guaranteed. The main benefit of our approach is to preserve the local IP performances when encapsulating them. This approach is part of the RNRT ALIPTA project which targets design automation of intensive digital signal processing systems with GAUT, a high-level synthesis tool.

Published in:

Digital System Design, 2005. Proceedings. 8th Euromicro Conference on

Date of Conference:

30 Aug.-3 Sept. 2005