By Topic

Low-power and high-stability SRAM technology using a laser-recrystallized p-channel SOI MOSFET

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Takao, Y. ; Fujitsu Ltd., Kawasaki, Japan ; Shimada, H. ; Suzuki, N. ; Matsukawa, Y.
more authors

Laser recrystallization of p-channel SOI MOSFETs on an undulated insulating layer is demonstrated for SRAMs with low power and high stability. Self-aligned p-channel SOI MOSFETs for loads are stacked over bottom n-channel bulk MOSFETs for both drivers and transfer gates. A sufficient laser power assures the same leakage currents between SOI MOSFETs fabricated on an undulated insulating layer in memory cell regions and on an even insulating layer in field regions. The on/off ratio of the SOI MOSFETs is increased by a factor of 104, and the source-drain leakage current is decreased by a factor of 10-102 compared with those of polysilicon thin-film transistors (TFTs) fabricated by using low-temperature regrowth of amorphous silicon. A test 256-kb SRAM fabricated this technology shows improved stand-by power dissipation and cell stability. The process steps can be decreased to 83% of those TFT load SRAMs if both the peripheral circuit and memory cells are made with p-channel SOI and n-channel bulk MOSFETs

Published in:

Electron Devices, IEEE Transactions on  (Volume:39 ,  Issue: 9 )