Biologically plausible VLSI neural network implementation with asynchronous neuron and spike-based synapse

This paper describes a new asynchronous spike based neural networks VLSI implementation, inspired by the biological plausibility and low power requirement. The voltage-controlled linear conductance produces the synaptic function of multiplication, weight programming, and summation of synaptic spike currents for the neuron. The operation speed of synaptic computation is up to 300 Mega operations with a small power consumption of 33 microwatts. The overall power consumption can be less in real applications, as individual synapse only consumes the power when there is an active neural input. The neuron is based on multiple combinations of synapses and the HSPICE simulation demonstrates the asynchronous spike behavior of integration-and-firing with a refractory period. The advantages of asynchronous operation, removal of reference clocks, and low voltage operation are exhibited compared to previous pulse-based analogue-mixed neural networks VLSI. The asynchronous spike based neural networks in 0.18μm CMOS VLSI technology is proposed to provide the advantage of analogue-mixed neural network VLSI with small power consumption and no need for a synchronous operation.