Cart (Loading....) | Create Account
Close category search window
 

A fully integrated 24 GHz fractional PLL with a low-power synchronized ring oscillator divider

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)
Mazouffre, O. ; IXL Lab., Univ. of Bordeaux 1, Talence, France ; Lapuyade, H. ; Begueret, J. ; Cathelin, A.
more authors

This paper presents the design and the experimental measurements of a 24 GHz fully integrated fractional PLL with a new low power prescaler. This circuit is implemented in a 0.25 μm SiGe:C process from STMicroelectronics (BiCMOS7RF). The PLL power dissipation is 148 mW and fulfills a 24.8 to 26.8 GHz frequency locking range, while exhibiting a phase noise of -97 dBc/Hz at 100 kHz from the carrier. The simulated PLL unity-gain bandwidth is 27 MHz, with a phase margin of 56 °. The PLL uses a new latch-based prescaler (SRO) which exhibits a very low power dissipation of 0.74 GHz/mW.

Published in:

Bipolar/BiCMOS Circuits and Technology Meeting, 2005. Proceedings of the

Date of Conference:

9-11 Oct. 2005

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.