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High-Performance On-Chip Interconnect Circuit Technologies for sub-65nm CMOS

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1 Author(s)
Kaul, H. ; Circuit Res. Lab., Intel Corp., Hillsboro, OR

The continued increase in performance and integration levels of VLSI designs for the last three decades has been fueled by shrinking transistor sizes. Unlike devices, on-chip wires get slower with technology scaling and pose performance and power challenges as VLSI designs scale into the nanometer regime. At the same time signal integrity issues have also become important due to increased cross-talk and inductive effects and pose reliability challenges for on-chip signaling. In this tutorial the authors discussed various techniques for improving performance, energy-efficiency and signal integrity of on-chip signaling. The scope of these techniques includes solutions at the architectural, circuit and physical design level

Published in:

SOC Conference, 2005. Proceedings. IEEE International

Date of Conference:

19-23 Sept. 2005