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Dynamic fraction control bus: new SOC on-chip communication architecture design

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2 Author(s)
Nan Wang ; Center for Adv. Comput. Studies, Louisiana Univ., Lafayette, LA, USA ; Bayoumi, M.A.

As technology scales toward deeper submicron, the integration of a large number of IP blocks on the same silicon die is becoming technically feasible. The on-chip communication architecture is becoming the bottleneck for these system-on-a-chips (SOC). The conventional communication architectures all have their limitations. This paper presents new communication architectures, static fraction control bus (SFCB) and dynamic fraction control bus (DFCB), to address the shortcomings of these conventional communication architectures.

Published in:

SOC Conference, 2005. Proceedings. IEEE International

Date of Conference:

25-28 Sept. 2005