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Efficient VLSI Architecture for Real-Time Motion Estimation in Advanced Video Coding

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3 Author(s)
Dias, T. ; DEETC-ISEL, INESC-ID, Lisbon ; Roma, N. ; Sousa, L.

This paper proposes a new scalable and efficient VLSI architecture for sub-pixel motion estimation. Based on this architecture, a modular and fully configurable motion estimation co-processor is also presented. The efficiency of such processing structure was assessed by embedding this circuit in a half-pixel accurate hierarchical motion estimation system using a two-step search procedure. Experimental results using FPGA devices show that the proposed motion estimation co-processor allows the estimation of motion vectors with half-pixel accuracy in real-time for the 4CIF image format

Published in:

SOC Conference, 2005. Proceedings. IEEE International

Date of Conference:

19-23 Sept. 2005