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Design study of (2 x 2) core architecture for matrix multiplications via programmable graph architecture

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5 Author(s)
Jun-Hee Mun ; Dept. of Electr. & Comput. Eng., Stony Brook Univ., NY ; Peng, M. ; Sangjin Hong ; Doboli, A.
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This paper presents a 2 times 2 core architecture for matrix multiplications via the programmable graph architecture approach proposed earlier. A larger matrix-matrix multiplication can be carried out through sub-matrix decomposition. The iterative operation is completely performed with simple arithmetic operations and memory accesses. The core architecture is structurally described using Verilog and its functionality has been verified. Performance of the operation and factors influencing the execution are analyzed

Published in:

SOC Conference, 2005. Proceedings. IEEE International

Date of Conference:

19-23 Sept. 2005

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