Cart (Loading....) | Create Account
Close category search window

Sub-10 nm gate length metal/high-k SOI MOSFETs with NiSi/sub 2/ [111]-facetted full silicide source/drain

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)

Metal/high-k SOI MOSFETs with NiSi2/Si (111)-facetted FUSI S/D are promising for aggressively scaled devices down to sub-10 nm gate length. The facet junction technique that we have developed works more effectively as the gate length becomes smaller. This device concept can be applied to 3D structures such as FinFETs, and it can also relieve the scaling of SOI thickness

Published in:

Device Research Conference Digest, 2005. DRC '05. 63rd  (Volume:1 )

Date of Conference:

22-22 June 2005

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.