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Extensible linear floating point SIMD neurocomputer array processor

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2 Author(s)
Means, R.W. ; HNC Inc., San Diego, CA, USA ; Lisenbee, L.

A 32-bit IEEE floating-point-format single-input-multiple-data (SIMD array processor) connected in a linear ring structure has been designed for neural network applications. The first prototype is composed of a SIMD array of between 16 and 64 cells. Each cell in the array is capable of simultaneously performing 20 million floating point multiplications and 20 million floating point arithmetic operations per second. This gives the prototype a peak processing performance of between 640 and 2560 MFLOPS. This compact array processor uses VLSI technology to produce four 32-bit cells per chip and off-the-shelf bit-slice components to assemble the controller. The hardware architecture of the SIMD neurocomputer array processor systolic array processor is described

Published in:

Neural Networks, 1991., IJCNN-91-Seattle International Joint Conference on  (Volume:i )

Date of Conference:

8-14 Jul 1991