3D image segmentation is one of the most demanding tasks in image processing. The applications comprise industrial and scientific tasks. Due to the high data volume advanced algorithms cannot be processed on standard hardware in real time. We propose the perfectly parallelizable 3D grey-value structure code (3D-GSC) for image segmentation on a new FPGA custom machine. This 128-bit FPGA co-processing board features an up-to-date Virtex-II Pro architecture, two large independent DDR-SDRAM channels, two fast independent ZBT-SRAM channels, and PCI-X bus and CameraLink interfaces. The hardware speeds up the segmentation algorithm and allows processing of a 5123 image (16 bpv) in about 2 sec
Published in:
Real Time Conference, 2005. 14th IEEE-NPSS
Date of Conference: 10-10 June 2005