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65nm high performance SRAM technology with 25F2 0.16μm2 S3 (stacked single-crystal Si) SRAM cell, and stacked peripheral SSTFT for ultra high density and high speed applications

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13 Author(s)
Hoon Lim ; R & D Center, Samsung Electron., Yongin, South Korea ; Soon-Moon Jung ; Youngseop Rah ; Taehong Ha
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For the first time, the 65nm high performance transistor technology and the highly compacted double stacked S3 SRAM cell with a size of 25F2, and 0.16μm2 has been combined for providing the high density and high density solutions which can make the breakthrough in the field of the cache memory products and the network memory products. The SSTFT (single-crystal silicon thin film transistor) is used not only for cell transistors but also for peripheral transistors. The selective Co silicidation techniques is developed for low resistance. By utilizing this technology, the high performance 288Mb synchronous SRAM product will be fabricated.

Published in:

Solid-State Device Research Conference, 2005. ESSDERC 2005. Proceedings of 35th European

Date of Conference:

12-16 Sept. 2005