65nm high performance SRAM technology with 25F2 0.16μm² S³ (stacked single-crystal Si) SRAM cell, and stacked peripheral SSTFT for ultra high density and high speed applications

For the first time, the 65nm high performance transistor technology and the highly compacted double stacked S³ SRAM cell with a size of 25F², and 0.16μm² has been combined for providing the high density and high density solutions which can make the breakthrough in the field of the cache memory products and the network memory products. The SSTFT (single-crystal silicon thin film transistor) is used not only for cell transistors but also for peripheral transistors. The selective Co silicidation techniques is developed for low resistance. By utilizing this technology, the high performance 288Mb synchronous SRAM product will be fabricated.