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A CMOS smart temperature sensor with a 3σ inaccuracy of ±0.1°C from -55°C to 125°C

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3 Author(s)
Pertijs, M.A.P. ; Electron. Instrum. Lab., Delft Univ. of Technol., Netherlands ; Makinwa, K.A.A. ; Huijsing, J.H.

A smart temperature sensor in 0.7 μm CMOS is accurate to within ±0.1°C (3σ) over the full military temperature range of -55°C to 125°C. The sensor uses substrate PNP transistors to measure temperature. Errors resulting from nonidealities in the readout circuitry are reduced to the 0.01°C level. This is achieved by using dynamic element matching, a chopped current-gain independent PTAT bias circuit, and a low-offset second-order sigma-delta ADC that combines chopping and correlated double sampling. Spread of the base-emitter voltage characteristics of the substrate PNP transistors is compensated by trimming, based on a calibration at one temperature. A high trimming resolution is obtained by using a sigma-delta current DAC to fine-tune the bias current of the bipolar transistors.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:40 ,  Issue: 12 )