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A 12.5-mb/s to 2.7-Gb/s continuous-rate CDR with automatic frequency acquisition and data-rate readback

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9 Author(s)
Dalton, D. ; Analog Devices, Limerick, Ireland ; Chai, K. ; Evans, E. ; Ferriss, M.
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A continuous-rate clock and data recovery (CDR) circuit that operates from 12.5 Mb/s to 2.7 Gb/s is described. The circuit automatically detects a change in input data rate, acquires the new frequency, and reports the data rate to the user without the need for an external reference clock or any programming. At 2.5Gb/s, it achieves an acquisition time of 1 ms. In tracking mode, it uses a dual DLL/PLL to provide superior jitter performance compared to a standard second-order loop. At the OC48 data rate, it achieves a jitter transfer bandwidth of 500 kHz and a jitter tolerance bandwidth of 3 MHz. It is on a 0.35-μm double-poly, triple-metal (DPTM) BiCMOS process, dissipates 235 mA from a 3.3-V supply, and occupies 9 mm2. It is in a compact 5×5 mm2 LFCSP package.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:40 ,  Issue: 12 )

Date of Publication:

Dec. 2005

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