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A 2×40 W class D amplifier chip is realized in 0.6-μm BCDMOS technology, integrating two delta-sigma (ΔΣ) modulators and two full H-bridge switching output stages. Analog feedback from H-bridge outputs helps achieve 67-dB power supply rejection ratio, 0.001% total harmonic distortion, and 104-dB dynamic range. The modulator clock rate is 6 MHz, but dynamically adjusted quantizer hysteresis reduces output data rate to 450 kHz, helping achieve 88% power efficiency. At AM radio frequencies, the modulator output spectrum contains a single peak, but is otherwise tone-free, unlike conventional pulse-width modulation (PWM) modulators which contain energetic tones at harmonics of the PWM clock frequency.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:40
,
Issue:
12
)
Date of Publication: Dec. 2005
- Page(s):
- 2388 - 2397
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 8675575
- Digital Object Identifier :
- 10.1109/JSSC.2005.856266
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 05 December 2005
- Issue Date :
- Dec. 2005
- Sponsored by :
- IEEE Solid-State Circuits Society
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