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Integrated stereo ΔΣ class D amplifier

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5 Author(s)
Gaalaas, E. ; Analog Devices Inc., Wilmington, MA, USA ; Bill Yang Liu ; Nishimura, N. ; Adams, R.
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A 2×40 W class D amplifier chip is realized in 0.6-μm BCDMOS technology, integrating two delta-sigma (ΔΣ) modulators and two full H-bridge switching output stages. Analog feedback from H-bridge outputs helps achieve 67-dB power supply rejection ratio, 0.001% total harmonic distortion, and 104-dB dynamic range. The modulator clock rate is 6 MHz, but dynamically adjusted quantizer hysteresis reduces output data rate to 450 kHz, helping achieve 88% power efficiency. At AM radio frequencies, the modulator output spectrum contains a single peak, but is otherwise tone-free, unlike conventional pulse-width modulation (PWM) modulators which contain energetic tones at harmonics of the PWM clock frequency.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:40 ,  Issue: 12 )

Date of Publication:

Dec. 2005

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