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This paper reviews soft error rate (SER) mitigations with standard process modifications in up-to-date commercial CMOS SRAMs and flip-flops. Acting in the front-end or middle-end levels, the following technology options are mainly evaluated: well engineering, partially and fully depleted silicon-on-insulator (FD SOI), and MIM capacitors. SER robustness gains are compared for eight classical process options based on original and published data. The best hardening efficiencies for SRAMs arise from the addition of stacked capacitors and the use of partially depleted (PD) SOI. SER trends are also reported for FD SOI and dual gates.