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Circuit-level modeling of soft errors in integrated circuits

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2 Author(s)
Walstra, S.V. ; Intel Corp., Santa Clara, CA, USA ; Changhong Dai

This paper describes the steps necessary to develop a soft-error methodology that can be used at the circuit-simulation level for accurate nominal soft-error prediction. It addresses the role of device simulations, statistical simulation, analytical soft-error rate (SER) model development, and SER-model calibration. The resulting approach is easily automated and generic enough to be applied to any type of circuit for estimation of the nominal SER.

Published in:

Device and Materials Reliability, IEEE Transactions on  (Volume:5 ,  Issue: 3 )