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Thermal-aware test scheduling and hot spot temperature minimization for core-based systems

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3 Author(s)
Chunsheng Liu ; Comput. & Electron. Eng., Nebraska-Lincoln Univ., Omaha, NE, USA ; K. Veeraraghavan ; V. Iyengar

Chip overheating has become a critical problem during test of today's complex core-based systems. In this paper, we address the overheating problem by incorporating thermal constraints in the test scheduling of core-based systems. We propose two algorithms for which the objective is to spread heat more evenly over the chip and reduce hot spots. The first uses the layout information to guide test scheduling, while the second relies on a progressive weighting mechanism. Experimental results show that the proposed thermal-constrained methods can not only guarantee a thermal-safe test schedule, but also reduce hot spot temperatures, leading to a balanced thermal distribution across the chip during test.

Published in:

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)

Date of Conference:

3-5 Oct. 2005