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SRAM-based field programmable gate arrays (FPGAs) are very susceptible to single event upsets (SEUs) that may have dramatic effects on the circuits they implement. In this paper, we present a design flow composed by both standard tools, and ad-hoc developed tools, which designers can use fruitfully for developing circuits resilient to SEUs. Experiments are reported on both benchmarks circuits and on a realistic circuit to show the capabilities of the proposed design flow.
Date of Conference: 3-5 Oct. 2005