By Topic

Improving transition delay fault coverage using hybrid scan-based technique

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Ahmed, N. ; ASIC Product Dev. Center, Texas Instruments India, Bangalore, India ; Tehranipoor, M.

This paper presents a hybrid scan-based transition delay fault test. The proposed technique controls a small subset of scan cells by launch-off-shift method and the rest by launch-off-capture method. An efficient ATPG-based controllability measurement approach is proposed to select the scan cells to be controlled by launch-off-shift or launch-off-capture. In this technique, local scan enable signals are generated on-chip using two local scan enable generator cells. The cells can be inserted anywhere in a scan chain and the area overhead is negligible. The launch and capture information of scan enable signals are transferred into the scan chain during scan-in process. Our technique improves the fault coverage and reduces the pattern count and the scan enable design effort. The proposed hybrid technique is practice-oriented and implemented using current commercial ATPG tools.

Published in:

Defect and Fault Tolerance in VLSI Systems, 2005. DFT 2005. 20th IEEE International Symposium on

Date of Conference:

3-5 Oct. 2005