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High speed all digital symbol timing recovery based on FPGA

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4 Author(s)
Zhang Jian ; Dept. of Electr. Eng., Beijing Inst. of Technol., China ; Wu Nan ; Kuang Jingming ; Wang Hua

This paper presents an all digital timing recovery scheme for high speed modem. Compared to the conventional schemes, which use a VCO to drive A/D sampling clock, the new scheme based on interpolation filter is easy to simulate and implement. In the case which oversampling rate is slightly larger than 2, the new scheme can also give precise timing recovery. So this scheme is very suitable for high symbol rate situation. Firstly, the theory of the asynchronous symbol timing recovery is presented. Then, an implementation scheme of all digital timing recovery is proposed. As a key component, interpolation filter and timing controller are analyzed. Finally, based on the Xilinx Virtex II series FPGA xc2v1000-5, an all digital QPSK timing recovery scheme is implemented. Simulation and hardware test results show that the new scheme can efficiently be used when the symbol rate is up to 45 Msps.

Published in:

Wireless Communications, Networking and Mobile Computing, 2005. Proceedings. 2005 International Conference on  (Volume:2 )

Date of Conference:

23-26 Sept. 2005

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