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For adopting a mixed-mode approach for an array processor implementation, the reuse of analog components is one of the main motivations. This paper describes a modification of a previously presented ADC, in which the two most significant bits of the conversion are generated with the help of a ranked order filter and some additional logic. This strategy saves area in the ADC by efficient reuse of the large analog transistors of the ranked order filter. The converter structure along with simulations in a 0.18 μm digital CMOS technology are shown.