We are currently experiencing intermittent issues impacting performance. We apologize for the inconvenience.
By Topic

A modified in-cell ADC using ranked order extraction

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Vesalainen, L. ; Lab. of Microelectron., Turku Univ., Finland ; Poikonen, J. ; Paasio, A.

For adopting a mixed-mode approach for an array processor implementation, the reuse of analog components is one of the main motivations. This paper describes a modification of a previously presented ADC, in which the two most significant bits of the conversion are generated with the help of a ranked order filter and some additional logic. This strategy saves area in the ADC by efficient reuse of the large analog transistors of the ranked order filter. The converter structure along with simulations in a 0.18 μm digital CMOS technology are shown.

Published in:

Cellular Neural Networks and Their Applications, 2005 9th International Workshop on

Date of Conference:

28-30 May 2005